Google’s Tensor Processing Unit (TPU) — a chip custom-built for its machine learning framework, TensorFlow — is heading to edge devices. Today at the Cloud Next conference in San Francisco, the Mountain View company announced Edge TPU, an architecture tailor-made for industrial manufacturing and internet of things devices.
Edge TPUs aren’t quite like the chips that accelerate algorithms in Google’s data centers — those TPUs, the third generation of which the company announced at its I/O Developer conference in May, are liquid-cooled and designed to slot into server racks. They’ve been used internally to power products like Google Photos, Google Cloud Vision API calls, and Google Search results.
By contrast, Edge TPUs, which measure about a fourth of a penny in size, run calculations offline and locally, supplementing traditional microcontrollers and sensors. And they don’t train machine learning models — instead, they run inference (prediction) with a lightweight, low-overhead version of TensorFlow that’s more power efficient than the full-stack framework.
That said, both TPUs are cut from the same cloth — they’re application-specific integrated circuits (ASICs), programmable chips optimized for specific workloads. That makes them highly efficient at performing tasks like training machine learning models from datasets (in the Cloud TPU’s case) and executing those models on-device (the Edge TPU’s function).
Edge TPUs will be made available in October in a modular reference board consisting of an Edge TPU, an NXP…